The increased complexity of spacecraft and aircraft as well as other vehicles has resulted in a need to incorporate more and more electronic systems in such vehicles. However, the complexity has reached a point where the required and desired electronic systems exceed the available space in the vehicle to accept all such systems. In order to overcome this problem, numerous efforts have and are being made to reduce the size of the electronic packages that make up such electronic systems.
Electronic system evolution has followed the trend of producing more functionality in less volume, at lower weight, and lower cost. Improvements in integrated circuit chip density and functionality have mostly contributed toward improved efficiency, however, advancements in packaging of these devices have also been beneficial. As it becomes more difficult to achieve substantial improvements through integrated circuit technology advances, new packaging approaches have become necessary to obtain density improvements and to allow the full performance potential of interconnected chips to be used.
The term "chip" in this description refers to an electrically functional integrated circuit die. The active face of the chip is defined as the surface on which the integrated electronics have been disposed. The back side refers to the surface opposite the active face.
It is known to place an integrated circuit chip in a plastic package for protection and then solder the package to a substrate. Typical integrated circuit packages contain only one chip. The package is substantially larger than the chip, thereby limiting the overall packaging density. Conventional packaging systems employing printed circuit boards with single chip packages are unable to provide the required number of chips within a volume and weight which is compatible with the needs of advanced circuit applications.
The present invention relates to integrated circuitry packaging to increase its functional density, through use of a three-dimensional assembly arrangement, and to reduce material and assembly costs. Applications which require large memory capacity suffer from excessive packaging overhead when single chip packages are used.
This invention provides for the disposition of chips in a three dimensional configuration. This invention includes multiple arrays of stacked chips contained on both sides of a substrate. The techniques of this invention are applicable for use with any form of commercially available memory chip.
A three dimensional integrated circuit assembly is provided to solve the foregoing problems that includes a primary substrate with integrated circuit chips and means for allowing mechanical and electrically functional attachment of integrated circuit chips to both sides of the substrate using flip chip assembly techniques. In addition, one or more secondary substrates are provided comprising a printed flexible wiring substrate with a means for allowing mechanical and electrically functional attachment of integrated circuit chips to one side of the flexible substrate using flip-chip assembly techniques. The back sides of the chips on both the primary and secondary substrates are aligned and bonded together so as to allow additional use of the vertical space above or below the primary substrate. This creates a three dimensional arrangement of chips for more effective use of substrate area and allows more chips to be contained in a given volume. The secondary substrate additionally provides an interconnect to the primary substrate for its stacked chips through printed circuitry and termination leads to the primary substrate. The circuit packages described herein increase the density (volumetric efficiency) over existing approaches in order to provide higher density, lower weight, and improved functional performance for electronic systems.